1. Field of the Invention
This invention relates to a semiconductor device and its manufacturing method, and especially those using nitride III-V compound semiconductors such as gallium nitride (GaN).
2. Description of the Related Art
Nitride III-V compound semiconductors constraining GaN as the major component are direct transitional semiconductors having forbidden band widths ranging from 1.9 eV to 6.2 eV and enabling realization of light emitting devices theoretically capable of emitting light over a wide range from the visible spectrum to the ultraviolet. For these properties, semiconductor light emitting devices using GaN semiconductors have been placed under active developments. Additionally, GaN semiconductors have a large possibility as material of electron mobility devices. Saturation electron velocity of GaN is approximately 2.0.times.10.sup.7 cm/s, which is larger than those of GaAs and SiC, and its breakdown electric field is as large as approximately 5.times.10.sup.6 V/cm next to the intensity of diamond. For these natures, GaN semiconductors have been expected to be greatly hopeful as materials of high-frequency, high-power semiconductor devices.
For manufacturing transistor using such a GaN semiconductor, it is necessary to grow the GaN semiconductor by chemical vapor deposition (CVD) or molecular beam epitaxy (MBE), and a sapphire substrate is often used as the substrate therefor. However, although thermal conductivity of GaN at the room temperature is 1.3 W/cmK and larger than thermal conductivity 0.3 W/cmK of GaAs at the room temperature, thermal conductivity of sapphire at the room temperature is 0.4 W/cmK similarly to that of GaAs, and as small as approximately 1/12 when compared with thermal conductivity 4.9 W/cmK of SiC at the room temperature. Therefore, it has been pointed out that a GaN field effect transistor (FET) for a high output power made by growing a GaN semiconductor on a sapphire substrate was especially bad in heat dissipation during operation and was liable to deteriorate in characteristics ((1) Inst. Phys. Conf. Ser. No. 142, 765 (1996)). Therefore, improvement of heat dissipation characteristics is indispensable to ensure a high output power of a GaN FET. On the other hand, for operating the GaN FET at a high frequency its source inductance has to be reduced.
As basic technologies for realizing GaAs FETs for higher operative frequencies and higher output power relying reduction of the source inductance, there have conventionally been techniques for thinning a GaAs substrate, and techniques for making a via hole in a GaAs substrate and making electric connection to the source from the bottom surface of the substrate through the via hole. These techniques are summarized below ((2) Fundamentals of GaAs Field Effect Transistors, Denshi Joho Tsushin Gakkai, 1992, p.207; (3) U.S. Pat. No. 4,015,278; (4) Int. Electron Device Meet., Tech. Dig., 676 (1981)).
For thinning a GaAs substrate, first conducted primary lapping using a granular abrasive material of SiC or alumina. Then, by using abrasive grains of a grain size of 1 .mu.m or less of CeO.sub.2, ZrO.sub.2, CrO.sub.2, or the like, the substrate is polished on a soft polisher such as synthetic resin or artificial leather to remove processing strain by lapping. As a result, the remainder depth of the processing strain is reduced to 10 .mu.m or less, but additional processing by wet etching may be applied. As to the via hole to be made in the GaAs substrate, since GaAs is readily dissolved by any of sulfuric acid/hydrogen peroxide solution or alkali solution, wet etching using such solution as the etchant is essentially sufficient for making the via hole. However, since side etching becomes large with wet etching and it is difficult to control the shape of the via hole, reactive ion etching (RIE) or ion milling is used normally. When using RIE for making the via hole, an etching rate as high as 50 to 100 .mu.m/hr can be obtained, and the via hole can be made easily, by using a mixed gas of CCl.sub.2 F.sub.2 and He as the etching gas and using a silicon oxide (SiO.sub.2) film or an organic resist film as the etching mask. Since GaAs substrates are readily processed either mechanically or chemically as mentioned above, high-frequency operation and high-power output of GaAs FETs have already been realized by thinning the substrate and making the via hole in the substrate.
However, it is difficult to employ the technique successfully used in GaAs FETs for thinning the substrate and making the via hole in the substrate also for fabrication of GaN FETs. As referred to above, sapphire substrates are often used for manufacturing GaN FETs. Sapphire, however, is much harder than GaAs, and it is extremely difficult to reduce the thickness of the sapphire substrate by using the above-explained conventional lapping technology. If it is forcibly thinned by lapping, it will large curve due to a lapping strain to be concave on the major surface side where the device should be made, and it will finally break down. Also regarding the via hole to be made in the sapphire substrate, since sapphire is very stable in chemical property, wet etching cannot be used without any effective etchant. As to dry etching by RIE, since its etching rate is as very low as several um/hr in maximum, and there is no etching mask having a selectivity acceptable for selective etching. Therefore, it is actually impossible to make the via hole with any of these methods. So, when making GaN FET on a sapphire substrate, it has been difficult to realize high-frequency operation and high-power output relying on thinning the substrate and making the via hole.
The above-made discussion applies to the case where GaN FET is made on a sapphire substrate. However, the same problem also lies in the case where GaN FET is made on a SiC substrate which is very had and chemically stable similarly to sapphire substrates.
On the other hand, FIG. 1 shows a conventional GaN semiconductor laser. As shown in FIG. 1, in the GaN semiconductor laser, sequentially stacked on a c-plane sapphire substrate 101 are a GaN buffer layer 102, n-type GaN contact layer 103, n-type AlGaN cladding layer 104, n-type GaN optical guide layer 105, active layer 106 with a Ga.sub.1-x In.sub.x N/Ga.sub.1-y In.sub.y N multi quantum well structure, p-type GaN optical guide layer 107, p-type AlGaN cladding layer 108 and p-type GaN contact layer 109. An upper-lying portion of the n-type GaN contact layer 103, n-type AlGaN cladding layer 104, n-type GaN optical guide layer 105, active layer 106 with the Ga.sub.1-x In.sub.x N/Ga.sub.1-y In.sub.y N multi quantum well structure, p-type GaN optical guide layer 107, p-type AlGaN cladding layer 108 and p-type GaN contact layer 109 have a mesa configuration of a predetermined width. Additionally, a p-side electrode 110 is made on the p-type GaN contact layer 109 in ohmic contact therewith, and an n-side electrode 111 is made in ohmic contact on a location of the n-type GaN contact layer 103 adjacent to the mesa portion.
However, in the conventional GaN semiconductor laser shown in FIG. 1, since the n-side electrode 111 is made on the location of the n-type GaN contact layer 103 adjacent to the mesa portion, the current supplied between the p-side electrode 110 and the n-side electrode 111 during operation must flow along the n-type GaN contact layer 103. Therefore, the current path was long, and this resulted in increasing the operation voltage. Moreover, Since the GaN semiconductor laser has a structure locating both the p-side electrode 110 and the n-side electrode 111 on the bottom surface of the substrate, it was impossible to use an apparatus used for assembling GaAs semiconductor lasers having the p-side electrode on the top surface of the substrate and the n-side electrode on the bottom surface of the substrate. Therefore, the GaN semiconductor laser required a special assembling apparatus, and this invited an increase of the manufacturing cost.